IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 321

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Global Reset
Global Reset
Table 6–18. Global Reset Block Parameters
Table 6–19. Global Reset Block I/O Formats
GND
Table 6–20. GND Block Parameters
Table 6–21. GND Block I/O Formats
© June 2010 Altera Corporation
Specify Clock
Clock
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Specify Clock
Clock
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
O1
[L].[R]
[L].[R]
Name
Name
[1].[0]
Table
[1].[0]
Table
Simulink (2),
Simulink (2),
is an input port. O1
is an input port. O1
6–19:
6–21:
On or Off
User defined (Parameterizable) Specifies the name of the required clock signal.
On or Off
User defined (Parameterizable) Specifies the name of the required clock signal.
The Global Reset (or SCLR) block provides a single bit reset signal. All signals
driven by the block are connected to the global reset for that clock domain. In
simulation, this block outputs a constant 0.
Table 6–18
Table 6–19
The GND block is a single bit that outputs a constant 0.
parameters.
Table 6–21
Figure 6–11
(3)
(3)
[L].[R]
[L].[R]
is an output port.
is an output port.
O1: out STD_LOGIC
O1: out STD_LOGIC
Value
Value
shows the Global Reset block parameters.
shows the Global Reset block I/O formats.
shows the GND block I/O formats.
shows a design example with the GND block.
(Note 1)
(Note 1)
Turn on to explicitly specify the clock name.
Turn on to explicitly specify the clock name.
Preliminary
VHDL
VHDL
Description
Description
Table 6–20
DSP Builder Standard Blockset Libraries
shows the GND block
Type
Explicit
Type
Explicit
6–13
(4)
(4)