IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 226

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–18
Table 2–26. Increment Decrement Block Parameters (Part 2 of 2)
Table 2–27. Increment Decrement Block I/O Formats
Figure 2–10. Increment Decrement Block Example
DSP Builder Standard Blockset Libraries
Direction
Starting Value
Clock Phase
Selection
Specify Clock
Clock
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
O1
[L].[R]
Name
[1]
[1]
[LP].[RP]
Table
Simulink (2),
is an input port. O1
2–27:
Increment,
Decrement
User Defined
(Parameterizable)
User Defined
On or Off
User defined
On or Off
On or Off
(3)
Table 2–27
Figure 2–10
[L].[R]
Value
I1: in STD_LOGIC
I2: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
is an output port.
shows the Increment Decrement block I/O formats.
shows an example with the Increment Decrement block.
Count up or down.
Enter the value with which to begin counting. This value is the initial output value
of the block after a reset.
Specify the phase selection with a binary string, where a 1 indicates the phase in
which the block is enabled. For example:
Turn on to explicitly specify the clock name.
Specify the clock signal name.
Turn on if you want to use the clock enable input (ena).
Turn on if you want to use the synchronous clear input (sclr).
1—The block is always enabled and captures all data passing through the
block (sampled at the rate 1).
10—The block is enabled every other phase and every other data (sampled at
the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second data
of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and
4 do not pass through the block.
(Note 1)
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Increment Decrement
Type
(4)