IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 361

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Single-Port RAM
Table 9–32. Shift Taps Block I/O Formats (Part 2 of 2)
Figure 9–11. Shift Taps Block Example
Single-Port RAM
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
….
O
…
On
O
[L].[R]
i[L1].[R1]
n+1[1]
[L1].[R1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–32:
Figure 9–11
The Single-Port RAM block maps data to an embedded RAM (embedded array
block, EAB; or embedded system block, ESB) in Altera devices. A single read/write
port allow simple access.
The Single-Port RAM block accepts any type as data input. The input port is
registered, and the output port can optionally be registered. The input address bus
must be Unsigned. The clock enable signal (ena) bypasses any output register.
The contents of the RAM are pre-initialized to zero by default. Use an Intel
Hexadecimal (.hex) file or a MATLAB array to specify them.
(3)
[L].[R]
is an output port.
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
….
Oi: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
….
On: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O
n+1
: out STD_LOGIC
shows an example with the Shift Taps block.
(Note 1)
Preliminary
VHDL
DSP Builder Standard Blockset Libraries
Type
Implicit
Explicit
9–21
(4)