IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 340

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–4
Table 8–4. Multiple Port External RAM Block Parameters
DSP Builder Standard Blockset Libraries
Number of Write Interfaces 0–5
Number of Read Interfaces 0–5
Data Width
Address Width
Wait States Per Write
Maximum Latency
Size
Offset
Notes to
(1) The size added to the offset must be less than 2
Table 8–4
Name
Table 8–4
8, 16, 32, 64,
or 128
1–32
0–10
1–255
1–2
1–2
n
n
Value
shows the Multiple Port External RAM block parameters.
(Note 1)
(Note 1)
n
where n is the address width.
Specifies the number of write ports.
Specifies the number of read ports.
Specifies a fixed number of wait states for each write transfer.
Specifies the latency for pipelined read transfers.
Specifies the number of bits for the data. No other values are supported. 64
and 128 bit data widths require a Simulink fixed-point license.
Specifies the number of bits n for the address.
Specifies the total size of the RAM in bytes (the number of addresses when
you use a range of addresses).
Specifies an offset for the RAM start address (the start address when you use
a range of addresses.
Preliminary
Description
© June 2010 Altera Corporation
Chapter 8: Simulation Library
Multiple Port External RAM