IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 170

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

12–2
HDL Import
MegaCore Functions
Memory Initialization Files
Exporting HDL
DSP Builder Standard Blockset User Guide
1
In general, source files that you import with HDL Import are not part of a DSP Builder
project. DSP Builder references them in projects that generate with the Export HDL
flow as external files, with absolute paths.
When you move a design to a new version of the tools or to a location on a different
computer, run the alt_dspbuilder_refresh_HDLimport script to ensure the
HDL Import blocks are up-to-date.
When migrating to a new computer, re-import the HDL to enable hardware
generation (although simulation in Simulink may be possible without this step).
The MegaCore IP Library always installs in the same parent directory as the Quartus
II installation. This directory is not a subdirectory of the quartus directory but a
relative path to an install directory at the same level as the quartus directory. The
expected directory structure is:
This feature allows the Export HDL flow to use relative paths, and improves
portability.
Before the Quartus II software version 8.0, it was possible to install previous versions
of the MegaCore IP Library in any specified location. If you use an old version of the
MegaCore IP Library in your design, there may still be absolute paths in the generated
Quartus II IP (.qip) files that you must modify when you move projects to a different
location. The .qip file contains all the assignments and other information that the
design requires to process the exported HDL in the Quartus II compiler and generate
hardware.
When moving a design to a new version of the tools or a different location, run the
alt_dspbuilder_refresh_megacore script to ensure that the MegaCore
function blocks are up-to-date.
Successful migration of designs with MegaCore Functions assumes that the new
environment has all the required IP installed. It may be necessary to install the
MegaCore IP Library and run the alt_dspbuilder_setup_megacore script.
Intel-format hexadecimal (.hex) files are required for memory initialization in
simulation and hardware generation. If they are generated by HDL Import or
MegaCore function blocks, ensure that they are in the import directory. This fact is
generally not the case if you generate the files with HDL Import.
You can export the DSP Builder-generated synthesizable HDL to a Quartus II project
and then use the Export tab in the Signal Compiler block to export them
(Figure
<install_path><QUARTUS_ROOTDIR>\..\ip
12–1).
Preliminary
© June 2010 Altera Corporation
HDL Import
Chapter :