IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 417

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

External RAM block
Extract Bit block
F
FIFO block
Flipflop block
Frequency
G
Gain block
Gate & Control library
Generating a Testbench
Global Reset (or SCLR) block
GND block
H
Hardware in the loop (HIL)
HDL
HDL Entity block
HDL export
HDL import
HDL Import block
HDL Input block
HDL Output block
Hierarchical design
HIL (Hardware in the Loop) block
How to Contact Altera
I
If Statement block
Increment Decrement block
© June 2010 Altera Corporation
Stratix EP1S80 board
Stratix II EP2S180 board
Stratix II EP2S60 board
Stratix II EP2S90GX PCI Express board
Stratix III EP3SL150 board (7-seg display)
Stratix III EP3SL150 board (HSMC A)
Stratix III EP3SL150 board (HSMC B)
Stratix III EP3SL150 board (LED/PB)
Subsystem Builder
Switch Control
Design Rules
Burst & frame modes
Design flow
Overview
Requirements
Troubleshooting
Walkthrough
Simulation model
Black box
Features
Updating
Walkthrough
2–15
9–10
6–13
12–2
1–2
8–1
3–24
4–10
5–1
5–1
6–12
1–7
3–8
5–3
8–1
1–4
5–2
4–11
1–5
1–8
13–4
3–20
8–1
5–10
3–16
4–1
Info–1
13–5
2–17
13–10
5–6
13–11
1–2
2–17
13–11
6–13
1–9
13–11
13–12
13–11
13–11
13–11
Preliminary
Input block
Integrator block
Interfaces library
IO & Bus library
L
LFSR Sequence block
Library
Logical Bit Operator block
Logical Bus Operator block
Logical Reduce Operator block
LUT (Look-Up Table) block
M
Magnitude block
Manual flow
MATLAB
MegaCore function
MegaCore Functions library
Memory block types
Memory Delay block
Model
AltLab
Arithmetic
Boards
Complex Type
Gate & Control
Interfaces
IO & Bus
MegaCore Functions
Rate Change
Simulation
State Machine Functions
Storage
Integration with
Opening the Simulink library browser
Using a base or masked subsystem variable
Using a MATLAB array to initilize a block
Design flow
Design issues
Device family
Generating a variation
Installing
Instantiating
OpenCore Plus evaluation
Optimizing
Parameterizing
Signal Compiler
Simulating
Simulating in the tutorial design
Updating variations
Version numbers
Walkthrough
DSP Builder Handbook Volume 2: DSP Builder Standard Blockset
1–2
1–1
11–1
6–14
9–1
3–19
6–1
4–1
5–1
2–1
8–1
4–3
4–3
2–19
4–2
6–1
7–1
4–2
5–1
2–20
4–3
4–13
4–14
3–1
4–1
1–3
4–3
1–3
4–14
1–1
9–13
4–14
4–1
4–2
12–1
4–16
4–3
4–17
9–11
12–1
10–1
4–1
4–19
4–8
2–4
Index–3
3–22
3–2