IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 236

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–28
Table 2–42. Parallel Adder Subtractor Block Parameters
Table 2–43. Parallel Adder Subtractor Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Number of Inputs
Add (+) Sub (–)
Enable Pipeline
Clock Phase Selection User Defined
Use Enable Port
Use Asynchronous
Clear Port
I/O
I
I1
….
Ii[
…
In[
I(n+1)
I(n+2)
[L1].[R1]
Li].[LiI]
Ln].[Rn]
Name
Simulink (2),
[1]
[1]
(3)
Table 2–41. Parallel Adder Subtractor Block Inputs and Outputs
Table 2–42
Table 2–43
data0–dataN
ena
aclr
r
>= 2
User Defined
On or Off
On or Off
On or Off
Value
Signal
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
…
Ii: in STD_LOGIC_VECTOR({Li + Ri - 1} DOWNTO 0)
….
In: in STD_LOGIC_VECTOR({Ln + Rn - 1} DOWNTO 0)
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
shows the Parallel Adder Subtractor block parameters.
shows the Parallel Adder Subtractor block I/O formats.
The number of inputs you want to use.
Specify addition or subtraction operation for each port with the operators + and –.
For example + – + implements a – b + c for 3 ports. However, two consecutive
subtractions, (– –) are not legal. Missing operators are assumed to be +.
When on, DSP Bu idler registers the output from each stage in the adder tree,
resulting in a pipeline length that is equal to ceil(log2(number of
inputs)).
When you enable a pipeline, you can indicate the phase selection with a binary
string, where a 1 indicates the phase in which the block is enabled. For example:
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
1—The block is always enabled and captures all data passing through the block
(sampled at the rate 1).
10—The block is enabled every other phase and every other data (sampled at
the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second data
of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and
4 do not pass through the block.
Input
Input
Input
Output
Direction
Preliminary
Operands.
Optional clock enable.
Optional asynchronous clear
Result.
VHDL
(Note 1)
Description
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Parallel Adder Subtractor
Type
Implicit
...
Implicit
...
Implicit
(4)