IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 99

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

SignalTap II Design Flow
© June 2010 Altera Corporation
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This chapter describes how to set up and run the SignalTap
chapter, you analyze three internal nodes in a simple switch controller design named
switch_control.mdl. This design flow works for any of the Altera development
boards that DSP Builder supports.
For detailed information about the supported development boards, refer to the Boards
Library chapter in the
DSP Builder Handbook.
In this design, an LED on the DSP development board turns on or off depending on
the state of user-controlled switches and the value of the incrementer. The design
consists of an incrementer function feeding a comparator, and four switches that feed
into two AND gates. The comparator and AND gate outputs feed an OR gate, which
feeds an LED on the DSP development board.
The SignalTap II logic analyzer captures the signal activity at the output of the two
AND gates and the incrementer of the design loads into the Altera device on the
development board. The logic analyzer retrieves the values and displays them in the
MATLAB work space.
For more information about using the SignalTap II logic analyzer with the Quartus II
software, refer to the Quartus II Help or to Volume 3 of the
A SignalTap II Logic Analyzer block in DSP Builder includes the following
characteristics:
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Alternatively, you can use the Quartus II software to instantiate of the SignalTap II
logic analyzer in your design. The Quartus II software supports additional features,
such as using multiple clock domains, and adjusting the percentage of data captured
around the trigger point.
Working with the SignalTap II logic analyzer in DSP Builder involves the following
flow:
1. Add a SignalTap II Logic Analyzer block to your design.
2. Specify the signals (nodes) that you want to analyze by inserting SignalTap II
3. Turn on the Enable SignalTap option in the Signal Compiler dialog box.
Has a simple, easy-to-use interface
Analyzes signals in the top-level design file
Uses a single clock source
Captures data around a trigger point. 88% of the data is pre-trigger and 12% of the
data is post-trigger
Node blocks.
6. Performing SignalTap II Logic Analysis
DSP Builder Standard Blockset Libraries
Preliminary
DSP Builder Standard Blockset User Guide
®
Quartus II
section in volume 2 of the
II logic analyzer. In this
Handbook.