IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 238

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–30
Table 2–45. Pipelined Adder Block Parameters
Table 2–46. Pipelined Adder Block I/O Formats
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[]
[].[number of bits]
Number of Pipeline
Stages
Direction
Use Enable Port
Use Asynchronous
Clear Port
Use Carry In Port
Use Overflow /
Carry Out Port
Use Direction Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
I6
O1
O2
[L].[R]
Name
[L].[R]
[L].[R]
[1]
[1]
[1]
[1]
[L].[R]
[1]
Table
Simulink (2),
is an input port. O1
2–46:
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
>= 0
(Parameterizable)
ADD, SUB
On or Off
On or Off
On or Off
On or Off
On or Off
(3)
Table 2–45
Table 2–46
Figure 2–18
[L].[R]
Value
I1: in STD_LOGIC_VECTOR({L + R} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L + R} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
I5: in STD_LOGIC
I6: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L + R} DOWNTO 0)
O2: out STD_LOGIC
is an output port.
shows the Pipelined Adder block parameters.
shows the Pipelined Adder block I/O formats.
shows an example with the Pipelined Adder block.
The bus number format that you want to use.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point. This option applies
only to signed fractional formats.
The number of pipeline stages.
Use the block as an adder or subtractor.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Turn on to use the carry in input (cin).
Turn on to use the overflow or carry out output (ovl).
Turn on to use the direction input (addsub). 1= add, 0 = subtract.
(Note 1)
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
Explicit
Type
Pipelined Adder
(4)