IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 59

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Frequency Design Rules
© June 2010 Altera Corporation
Figure 3–16
example MultipleClockDelay.mdl. Output clock PLL_clk0 is set to 800 ns, and
output clock PLL_clk1 is set to 100 ns.
Figure 3–16. PLL Setting
Datapath A (green in
B (red in
setting the Specify Clock option and enter the clock name in the Block Parameter
dialog box for each input block.
In this design, the Sample time parameters for the Sine Wave a block and Sine
Wave b block are set explicitly to 1e-006 and 1e-007, so that DSP Builder provides
data to the input blocks at the rate at which they sample.
Using Advanced PLL Features
The DSP Builder PLL block supports the fundamental multiplication and division
factor for the PLL. If you want to use other PLL features (such as phase shift, duty
cycle), use a separate Quartus II project with the following method:
■
■
■
Create a new Quartus II project and use the MegaWizard™ Plug-In to configure
the ALTPLL block.
Add the DSP Builder .mdl file to the Quartus II project as a source file.
Create a top-level design that instantiates your ALTPLL variation and your DSP
Builder design.
Figure
shows the clock setting configuration for the PLL block in the design
3–15) operates on output clock PLL_clk1. Specify these clocks by
Figure
Preliminary
3–15) operates on output clock PLL_clk0 and datapath
DSP Builder Standard Blockset User Guide
3–15