IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 231

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Multiply Accumulate
Table 2–34. Multiplier Block Input/Output Ports
Figure 2–14. Multiplier Block Example
Multiply Accumulate
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
O2
[L].[R]
[L].[R]
[L].[R]
[1]
[1]
[Lo].[Ro]
[Lo].[Ro]
Table
Simulink (2),
is an input port. O1
f
2–34:
(3)
Figure 2–14
For more information about multiplier operations, refer to the
User
The Multiply Accumulate block consists of a single multiplier feeding an
accumulator, which performs the calculation y += a × b.
The input is signed integer, unsigned integer, or signed binary fractional formats.
Table 2–35
Table 2–35. Multiply Accumulate Block Inputs and Outputs (Part 1 of 2)
a
b
sload
addsub
[L].[R]
Guide.
Signal
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I3: STD_LOGIC
I4: STD_LOGIC
O1: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0)
O2: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0)
is an output port.
shows the Multiply Accumulate block inputs and outputs.
shows an example with the Multiplier block.
Input
Input
Input
Input
Direction
(Note 1)
Preliminary
Operand A.
Operand B.
Synchronous load signal.
Optional accumulator direction (1= add, 0 = subtract).
VHDL
Description
DSP Builder Standard Blockset Libraries
Multiplier Megafunction
Explicit
Explicit
Explicit
Explicit
Type
(4)
2–23