IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 257

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Complex Product
Table 3–17. Complex Multiplexer Block I/O Formats
Figure 3–6. Complex Multiplexer Block Example
Complex Product
© June 2010 Altera Corporation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
O1
Imag(max(L1,L2)),(max(RI,R2))
[L].[R]
Real([L1].[R1])Imag([L1].[R1])
Real([L2].[R2])Imag([L2].[R2])
[1]
[1]
[1]
Real(max(L1,L2)),(max(RI,R2) )
Table
Simulink (2),
is an input port. O1
3–17:
Table 3–17
Figure 3–6
The Complex Product block performs output multiplication of two scalar complex
inputs. Operand a is multiplied by operand b and the result output on r as the
following equation shows:
(3)
[L].[R]
r = a × b
is an output port.
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I2Real: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0)
I2Imag: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
I5: in STD_LOGIC
O1Real: in STD_LOGIC_VECTOR({max(LI,L2) + max(RI,R2) - 1} DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({max(LI,L2) + max(RI,R2) - 1} DOWNTO 0)
shows the Complex Multiplexer block I/O formats.
shows an example with the Complex Multiplexer block.
(Note 1)
Preliminary
VHDL
DSP Builder Standard Blockset Libraries
Implicit
Implicit
Implicit
Type
(4)
3–11