IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 289

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-MM Master
Figure 5–3. Avalon-MM Blocks Example
Avalon-MM Master
Table 5–1. Signals Supported by the Avalon-MM Master Block (Part 1 of 2)
© June 2010 Altera Corporation
waitrequest
address
read
readdata
write
writedata
byteenable
endofpacket
Signal
Input
Output
Output
Input
Output
Output
Output
Input
Direction
Figure 5–3
The Avalon-MM Master block defines a collection of ports for connection to an
SOPC Builder system when your design functions as an Avalon-MM master interface.
Table 5–1
lists the signals supported by the Avalon-MM Master block.
This signal forces the master port to wait until you are ready to proceed with the
transfer.
The address signal represents a byte address but is asserted on word boundaries only.
Available with Read or Read/Write address type. Read request signal. Not required if
there are no read transfers. If used, also use readdata.
Available when Read or Read/Write address type is chosen. Data lines for read
transfers. Not required if there are no read transfers. If used, also use read.
Available when Write or Read/Write address type is chosen. Write request signal. Not
required if there are no write transfers. If used, also use writedata.
Available when Write or Read/Write address type is chosen. Data lines for write
transfers. Not required if there are no write transfers. If used, also use write.
Available when Write or Read/Write address type is chosen and the bit width is greater
than 8. Enables specific byte lane(s) during write transfers to memories of width greater
than 8 bits. All byteenable lines must be enabled during read transfers.
Available when Allow Flow Control is on. Indicates an end-of-packet condition.
shows an example model with Avalon-MM blocks.
Preliminary
Description
DSP Builder Standard Blockset Libraries
5–3