IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 264

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–2
Binary to Seven Segments
Table 4–3. Binary to Seven Segments Display Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
I
I/O
I1
[4].[0]
Simulink (2),
(3)
The Binary to Seven Segments block converts a 4-bit unsigned input bus to a
7-bit output for connection to a seven-segment displays.
The seven-segment display is set to display the hexadecimal representation of the
input number.
Table 4–1
Table 4–1. Binary to Seven Segments Block Inputs and Outputs
Table 4–2
Segments block.
Table 4–2. Binary to Seven Segments
Table 4–3
(3:0)
(6:0)
Binary
Signal
I1: in STD_LOGIC_VECTOR(3 DOWNTO 0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
shows the Binary to Seven Segments block inputs and outputs.
shows the 4-bit to 7-bit conversion performed by the Binary to Seven
shows the Binary to Seven Segments block I/O formats.
Input
Output
Direction
Decimal
Input
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Preliminary
4-bit data input.
7-bit data output.
VHDL
Hex
0
1
2
3
4
5
6
7
8
9
A
b
C
d
E
F
(Note 1)
Description
1000000
1111001
0100100
0110000
0011001
0010010
0000010
1111000
0000000
0010000
0001000
0000011
1000110
1000001
0000110
0001110
Binary
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Output
Binary to Seven Segments
Explicit
Type
Decimal
121
120
64
36
48
25
18
16
70
33
14
2
0
8
3
6
(4)