IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 50

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–6
Figure 3–4. Tap Delay Line in Quartus II Version RTL Viewer
Figure 3–5. 3-Tap FIR Filter Arithmetic Operation in Quartus II Version RTL Viewer
DSP Builder Standard Blockset User Guide
Arithmetic Operation
Figure 3–5
This design requires three multipliers and one parallel adder. The arithmetic
operations increase the bus width in the following ways:
■
■
The parallel adder has three input buses of 14, 16, and 14 bits. To perform this
addition in binary, DSP Builder automatically sign extends the 14-bit busses to 16 bits.
The output bit width of the parallel adder is 18 bits, which covers the full resolution.
where c[i] are the coefficients and x[k - i] are the data.
Multiplying a  b in SBF format (where l is left and r is right) is equal to:
The bus width of the resulting signal is:
Adding a + b + c in SBF format (where l is left and r is right) is equal to:
The bus width of the resulting signal is:
[la].[ra]  [lb].[rb]
([la] + [lb]).([ra] + [rb])
[la].[ra] + [lb].[rb] + [lc].[rc]
(max([la], [lb], [lc]) + 2).(max([ra], [rb], [rc]))
shows the arithmetic section of the filter, that computes the output yout:
Preliminary
yout k  
=
i

=
2
0
x k i –

c i  
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Bit Width Design Rule