IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 222

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–14
Table 2–20. DSP Block Parameters (Part 2 of 2)
Table 2–21. DSP Block I/O Formats
DSP Builder Standard Blockset Libraries
Output Saturation
Operation Type
Use Output Overflow Port
Register Data Inputs to the
Multiplier(s)
Register Output of the
Multiplier
Register Output of the
Adder
Register Chainout Adder
Register Shiftout
Use Enable Port
Use User Asynchronous
Clear Port
I/O
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1[
….
In
I(n+1)
I(n+2)
where 3 < n < 9
O1
[R1]
[L].[R]
[L1].[R1]
L1].[R1]
2 x [L1]
Table
Simulink (2),
is an input port. O1
Name
[1]
[1]
+ ceil(log2(n))
2–21:
1
Compilation in the Quartus II software requires that the input bit widths are 18 bits
when you use the chainout adder input, output rounding with an output LSB in the
range 6 to 21, or output saturation with an output MSB in the range 28 to 43.
Table 2–21
(3)
[L].[R]
.2 x
None (wrap),
Symmetric,
Asymmetric
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
On or Off
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
….
In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I(n+1): in STD_LOGIC
I(n+2): in STD_LOGIC
where 3 < n < 9
O1: out STD_LOGIC_VECTOR({(2 x L1) + ceil(log2(n)) + (2 x R1) - 1} DOWNTO 0) Implicit
Value
shows the DSP block I/O formats.
(Note 1)
You can disable (wrap), or enable saturation. Symmetric saturation
specifies that the absolute value of the maximum negative number is
equal to the maximum positive number. Asymmetric saturation specifies
that the absolute value of the maximum negative number is 1 greater than
the maximum positive number. Do not enable rounding unless you have
enabled saturation.
Turn on to use the overflow output for the saturation unit.
Turn on to create registers at the data inputs to the multiplier. (Always on
if in shiftin mode.)
Turn on to create a register at the data output from the multiplier.
Turn on to create a register at the output of the adder. (Always on if
accumulator mode is enabled.)
Turn on to create a register at the output of the chainout adder (if it is
used).
Registers the shiftouta output (if it is used).
Turn on to use the clock enable input (ena) if using registers.
Turn on to use the asynchronous clear input (aclr) if using registers.
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
...
Explicit
Type
(4)
DSP