IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 208
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 208 of 422
- Download datasheet (6Mb)
1–18
VCD Sink
Table 1–20. VCD Sink Block Parameters
Figure 1–7. Simulink Model With the VCD Sink Block
DSP Builder Standard Blockset Libraries
Number of Inputs
Name
An integer greater than 0 Specify the number of input ports on the VCD Sink block.
The VCD Sink block exports Simulink signals to a third-party waveform viewer.
When you run the simulation of your model, the VCD Sink block generates a value
change dump (.vcd) <VCD Sink block name>.vcd file, which a third-party waveform
viewer can read.
To use the VCD Sink block in your Simulink model, perform the following steps:
1. Add a VCD Sink block to your Simulink model.
2. Connect the simulink signals you want to display in a third-party waveform
3. Run the Simulink simulation.
4. Read the VCD file in the third-party waveform viewer.
If you use the ModelSim software to view waveforms, run the script
<VCD Sink block path>_vcd.tcl where the path is the hierarchical path of the block in
the Simulink model. That is: <model name>_<subsystem names>_<block name> each
separated by underscore character.
This Tcl script converts VCD files to ModelSim waveform format (.wlf), starts the
waveform viewer, and displays the signals. If you use any other third-party viewer,
load the VCD file directly into the viewer.
The VCD Sink block does not have any hardware representation and therefore does
not appear in the VHDL RTL representation created by the
Table 1–20
Figure 1–7
viewer to the VCD Sink block.
Value
shows the parameters for the VCD Sink block.
shows an example of the VCD Sink block
Preliminary
Description
Signal Compiler
© June 2010 Altera Corporation
Chapter 1: AltLab Library
VCD Sink
block.
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: