ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 209

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13. Power Manager (PM)
13.1
13.2
32142A–12/2011
Features
Overview
Rev: 4.2.0.4
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The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the
device, namely the CPU, and the modules and peripherals connected to the High Speed Bus
(HSB) and the Peripheral Buses (PBx).
The PM contains advanced power-saving features, allowing the user to optimize the power con-
sumption for an application. The synchronous clocks are divided into a number of clock
domains, one for the CPU and HSB, and one for each PBx. The clocks can run at different
speeds, allowing the user to save power by running peripherals relatively slow, whilst maintain-
ing high CPU performance. The clocks can be independently changed on-the-fly, without halting
any peripherals. The user may adjust CPU and memory speeds according to the dynamic appli-
cation load, without disturbing or re-configuring active peripherals.
Each module has a separate clock, enabling the user to save power by switching off clocks to
inactive modules. Clocks and oscillators can be automatically switched off during idle periods by
the CPU sleep instruction. The system will return to normal operation when interrupts occur.
To achieve minimal power usage, a special sleep mode, called Shutdown is available, where
power on all internal logic (CPU, peripherals) and most of the I/O lines is removed, reducing cur-
rent leakage. Only a small amount of logic, including the 32KHz crystal oscillator (OSC32K) and
the AST remain powered.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates hard and soft resets, and allows the reset source to be identified by software.
Generates clocks and resets for digital logic
On-the-fly frequency change of CPU, HSB and PBx clocks
Sleep modes allow simple disabling of logic clocks and clock sources
Module-level clock gating through maskable peripheral clocks
Wake-up from internal or external interrupts
Automatic identification of reset sources
Supports advanced Shutdown sleep mode
ATUC64/128/256L3/4U
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