ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 249

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5.4.1
14.5.4.2
14.5.4.3
14.5.4.4
32142A–12/2011
Enabling the DFLL
Internal synchronization
Disabling the DFLL
Open loop operation
Figure 14-2. DFLLIF Block Diagram
The DFLL is enabled by writing a one to the Enable bit (EN) in the DFLLn Configuration Register
(DFLLnCONF). No other bits or fields in DFLLnCONF must be changed simultaneously, or
before the DFLL is enabled.
Due to multiple clock domains in the DFLLIF, values in the DFLLIF configuration registers need
to be synchronized to other clock domains. The status of this synchronization can be read from
the Power and Clocks Status Register (PCLKSR). Before writing to a DFLLIF configuration reg-
ister, the user must check that the DFLLn Synchronization Ready bit (DFLLnRDY) in PCLKSR is
set. When this bit is set, the DFLL can be configured, and CLK_DFLL is ready to be used. Any
write to a DFLLIF configuration register while DFLLnRDY is cleared will be ignored.
Before reading the value in any of the DFLL configuration registers a one must be written to the
Synchronization bit (SYNC) in the DFLLn Synchronization Register (DFLLnSYNC). The DFLL
configuration registers are ready to be read when PCLKSR.DFLLnRDY is set.
The DFLL is disabled by writing a zero to DFLLnCONF.EN. No other bits or fields in DFLLn-
CONF must be changed simultaneously.
After disabling the DFLL, PCLKSR.DFLLnRDY will not be set. It is not required to wait for
PCLKSR.DFLLnRDY to be set before re-enabling the DFLL.
After enabling the DFLL, open loop mode is selected by writing a zero to the Mode Selection bit
(MODE) in DFLLnCONF. When operating in open loop mode the output frequency of the DFLL
will be determined by the values written to the Coarse Calibration Value field (COARSE) and the
Fine Calibration Value field (FINE) in the DFLLnCONF register. When writing to COARSE and
8+9
32
CSTEP
FSTEP
FMUL
IMUL
DFLLLOCKLOSTC
DFLLLOCKC
FREQUENCY
DFLLLOCKLOSTF
TUNER
DFLLLOCKF
COARSE
FINE
DFLLLOCKLOSTA
DFLLLOCKA
8
9
ATUC64/128/256L3/4U
DFLL
CLK_DFLLIF_DITHER
CLK_DFLLIF_REF
249