ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 636

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.7.13
Name:
Access Type:
Offset :
Reset Value:
• SET: Single Value Channel Set
Note:
32142A–12/2011
31
23
15
7
If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY.
If more than one ISCHSET register is present, ISCHSET0 controls channels 31 to 0 and ISCHSET1 controls channels 63 to 32.
The duty registers will be updated with the value stored in the ISDUTY register when any ISCHSETm register is written. Syn-
chronization takes place immediately when an ISCHSET register is written. The duty cycle registers will, however, not be
updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches.
Interlinked Single Value Channel Set
30
22
14
6
ISCHSETm
Write-only
0x30+m*0x10
0x00000000
29
21
13
5
28
20
12
4
SET
SET
SET
SET
27
19
11
3
ATUC64/128/256L3/4U
26
18
10
2
25
17
9
1
24
16
8
0
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