ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 744

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.9.17
Name:
Access Type:
Offset:
Reset Value:
• CHn: Channel N Status
32142A–12/2011
CH31
CH23
CH15
CH7
31
23
15
7
0: The corresponding channel is disabled.
1: The corresponding channel is enabled.
A bit in this register is cleared by writing a one to the corresponding bit in Channel Disable Register (CHDR).
A bit in this register is set by writing a one to the corresponding bit in Channel Enable Register (CHER).
The number of available channels is device dependent. Please refer to the Module Configuration section at the end of this
chapter for information regarding how many channels are implemented.
Channel Status Register
CH30
CH22
CH14
CH6
30
22
14
6
CHSR
Read-only
0x48
0x00000000
CH29
CH21
CH13
CH5
29
21
13
5
CH28
CH20
CH12
CH4
28
20
12
4
CH27
CH19
CH11
CH3
27
19
11
3
ATUC64/128/256L3/4U
CH26
CH18
CH10
CH2
26
18
10
2
CH25
CH17
CH9
CH1
25
17
9
1
CH24
CH16
CH8
CH0
24
16
8
0
744