ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 448

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.6.4.3
Figure 20-19. SPI Transfer Format (CPHA=1, 8 bits per transfer)
32142A–12/2011
SPI Master ->RXD
SPI Master ->TXD
SPI Master ->RTS
CLK cycle (for reference)
SPI Slave ->RXD
SPI Slave ->TXD
SPI Slave ->CTS
(CPOL= 0)
(CPOL= 1)
MOSI
MISO
CLK
NSS
CLK
Data Transfer
In SPI Slave Mode:
Table 20-7.
• The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK).
• The Clock Output Select bit (MR.CLKO) must be one.
• The BRGR.CD field must be at least 0x4.
• If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even,
• CLK frequency must be at least four times lower than the system clock.
• Up to nine data bits are successively shifted out on the TXD pin at each edge. There are no
ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART).
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL),
and SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits
are shifted and sampled, resulting in four non-interoperable protocol modes see
A master/slave pair must use the same configuration, and the master must be reconfigured if
it is to communicate with slaves using different configurations. See
MSB
1
MSB
SPI Bus Protocol Mode
SPI Bus Protocol Modes
2
6
6
0
1
2
3
3
5
5
4
4
4
5
3
3
CPOL
ATUC64/128/256L3/4U
0
0
1
1
6
2
2
7
1
1
Figures 20-19 and
8
LSB
LSB
CPHA
1
0
1
0
Table
20-20.
20-7.
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