ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 210

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.3
Figure 13-1. PM Block Diagram
13.4
Table 13-1.
13.5
13.5.1
13.5.2
13.5.3
32142A–12/2011
Name
RESET_N
Block Diagram
I/O Lines Description
Product Dependencies
Interrupt
Clock Implementation
Power Considerations
External Reset Pin
I/O Lines Description
Power-on Reset
Detector(s)
The PM interrupt line is connected to one of the interrupt controllers internal sources. Using the
PM interrupt requires the interrupt controller to be configured first.
In ATUC64/128/256L3/4U, the HSB shares source clock with the CPU. Write attempts to the
HSB Clock Select register (HSBSEL) will be ignored, and it will always read the same as the
CPU Clock Select register (CPUSEL).
The PM bus interface clock (CLK_PM) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. If disabled it can only be re-
enabled by a reset.
The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O lines“
power configuration.
Main Clock Sources
Description
Reset
Reset Sources
Interrupts
Clock Generator
Reset Controller
Sleep Controller
Type
Input
Synchronous
ATUC64/128/256L3/4U
Synchronous
CPU, HSB,
Instruction
Active Level
Low
Resets
clocks
Sleep
PBx
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