ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 479

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.7.12
Name:
Access Type:
Offset:
Reset Value:
• PDCM: Peripheral DMA Controller Mode
• DLC: Data Length Control
• WKUPTYP: Wakeup Signal Type
• FSDIS: Frame Slot Mode Disable
• DLM: Data Length Mode
• CHKTYP: Checksum Type
• CHKDIS: Checksum Disable
• PARDIS: Parity Disable
• NACT: LIN Node Action
Table 20-18.
32142A–12/2011
WKUPTYP
0
31
23
15
–
–
7
0: The LIN mode register is not written by the Peripheral DMA Controller.
1: The LIN mode register is, except for this bit, written by the Peripheral DMA Controller.
0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes.
0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal.
1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal.
0: The Frame Slot mode is enabled.
1: The Frame Slot mode is disabled.
0: The response data length is defined by DLC.
1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR).
0: LIN 2.0 “Enhanced” checksum
1: LIN 1.3 “Classic” checksum
0: Checksum is automatically computed and sent when master, and checked when slave.
1: Checksum is not computed and sent, nor checked.
0: Identifier parity is automatically computed and sent when master, and checked when slave.
1: Identifier parity is not computed and sent, nor checked.
NACT
LIN Mode Register
0
FSDIS
30
22
14
LINMR
Read-write
0x54
0x00000000
–
–
6
Mode Description
PUBLISH: The USART transmits the response.
DLM
29
21
13
–
–
5
CHKTYP
28
20
12
–
–
4
DLC
CHKDIS
27
19
11
–
–
3
ATUC64/128/256L3/4U
PARDIS
26
18
10
–
–
2
25
17
–
–
9
1
NACT
PDCM
24
16
–
8
0
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