ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 436

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.4
Table 20-2.
20.5
20.5.1
20.5.2
20.5.3
32142A–12/2011
Name
CLK
TXD
RXD
CTS
RTS
I/O Lines Description
Product Dependencies
I/O Lines
Clocks
Interrupts
I/O Lines Description
Description
Serial Clock
Transmit Serial Data
or Master Out Slave In (MOSI) in SPI master mode
or Master In Slave Out (MISO) in SPI slave mode
Receive Serial Data
or Master In Slave Out (MISO) in SPI master mode
or Master Out Slave In (MOSI) in SPI slave mode
Clear to Send
or Slave Select (NSS) in SPI slave mode
Request to Send
or Slave Select (NSS) in SPI master mode
The USART pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign these pins to their peripheral functions. Unused I/O lines may be
used for other purposes.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is required. If the hardware handshaking feature or modem mode is used, the internal pull up on
TXD must also be enabled.
The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USART before disabling the clock, to avoid freezing the USART in an undefined state.
The USART interrupt request line is connected to the interrupt controller. Using the USART
interrupt requires the interrupt controller to be programmed first.
ATUC64/128/256L3/4U
Output
Output
Type
Input
Input
I/O
Active Level
Low
Low
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