ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 627

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ATUC128L4U

Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC128L4U

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATUC128L4U-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATUC128L4U-AUT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
25.7.4
Name:
Access Type:
Offset :
Reset Value:
Note:
32142A–12/2011
SELn: Channel Select
31
23
15
7
The duty cycle of the PWMA channel SELn will be updated with the value stored in the DUTYn register when IMCHSEL is
written. If SELn points to a non-implemented channel, the write will be discarded.
The duty registers will be updated with the value stored in the DUTY3, DUTY2, DUTY1 and DUTY0 registers when the IMCH-
SEL register is written. Synchronization takes place immediately when an IMCHSEL register is written. The duty cycle registers
will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to
avoid glitches. When only 8 bits duty cycle value are considered for updating, the four duty cycle values can be written to the
IMDUTY register once. This is equivalent to writing the 8 bits four duty cycle values to the four DUTY registers one by one while
the upper 4 bits remain unchanged.
Interlinked Multiple Value Channel Select
30
22
14
6
IMCHSEL
Write-only
0x0C
0x00000000
29
21
13
5
28
20
12
4
SEL3
SEL2
SEL1
SEL0
27
19
11
3
ATUC64/128/256L3/4U
26
18
10
2
25
17
9
1
24
16
8
0
627

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