ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 31

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.5.1
4.5.2
32142A–12/2011
System Stack Issues
Exceptions and Interrupt Requests
relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384
bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),
not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up
appropriately. The same mechanisms are used to service all different types of events, including
interrupt requests, yielding a uniform event handling scheme.
An interrupt controller does the priority handling of the interrupts and provides the autovector off-
set to the CPU.
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
2. When a request is accepted, the Status Register and Program Counter of the current
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status
Register ensures that the core is returned to the previous execution mode when the
current event handling is completed. When exceptions occur, both the EM and GM bits
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address uniquely identifies the exception source.
ter file bank is selected. The address of the event handler, as shown in
page
34, is loaded into the Program Counter.
ATUC64/128/256L3/4U
Table 4-4 on
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