ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 775

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ATUC128L4U

Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC128L4U

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Part Number
Manufacturer
Quantity
Price
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Atmel
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32142A–12/2011
Figure 31-3. CAT Matrix Connections
In order to use the autonomous QTouch detection capability, the user must first set up the
Autonomous Touch Pin Select Register (ATPINS) and Autonomous/DMA Touch Configuration
Registers (ATCFG0 through 3) with appropriate values. The module can then be enabled using
the Control Register (CTRL). After the module is enabled, the module will acquire data from the
autonomous QTouch sensor and use it to determine whether the sensor is activated. The
active/inactive status of the autonomous QTouch sensor is reported in the Status Register (SR),
and it is also possible to configure the CAT to generate an interrupt whenever the status
changes. The module will continue acquiring autonomous QTouch sensor data and updating
autonomous QTouch status until the module is disabled or reset.
In order to use the DMATouch capability, it is first necessary to set up the pin mode registers
(PINMODE0, PINMODE1, and PINMODE2) so that the desired pins are specified as DMA-
Touch. The Autonomous/DMA Touch Configuration Registers (ATCFG0 through 3) must also be
configured with appropriate values. One channel of the Peripheral DMA Controller must be set
up to transfer state words from a block of memory to the DMATSW register, and another chan-
nel must be set up to transfer state words from the DMATSR register back to the same block of
memory. The module can then be enabled using the CTRL register. After the module is enabled,
the module will acquire count values from each DMATouch sensor. Once the module has
acquired a count value for a sensor, it will use a handshake interface to signal the Peripheral
DMA controller to transfer a state word to the DMATSW register. The module will use the count
value to update the state word, and then the updated state word will be transferred to the
DMATSR register. Another handshake interface will signal the Peripheral DMA controller to
transfer the contents of the DMATSR register back to memory. The status of the DMATouch
sensors can be determined at any time by reading the DMATouch Sensor Status Register
(DMATSS).
AVR32 Chip
ACREFN
VDIVEN
SMP
YK0
YK1
DIS
X2
X3
X6
X7
Y0
Y1
Rdis
Cs1 (Sense Capacitor)
Rsmp1
Cs0 (Sense Capacitor)
Ra
Rb
NOTE: If the CAT internal
current sources will be enabled,
the SMP signal and Rsmp
resistors should NOT be included
in the design. If the CAT internal
current sources will NOT be
enabled, the DIS signal and Rdis
resistor should NOT be included
in the design.
ATUC64/128/256L3/4U
QMatrix Sensor Array
Rsmp0
775

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