ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 467

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• CHMODE: Channel Mode
Table 20-11.
• NBSTOP: Number of Stop Bits
Table 20-12.
• PAR: Parity Type
Table 20-13.
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
32142A–12/2011
0
0
1
1
0
0
1
1
0
0
0
0
1
1
CHMODE
NBSTOP
If USART does not operate in SPI Mode (MODE is
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to change and which edge causes data to
be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK.
CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.
PAR
0
1
0
1
0
1
0
1
0
0
1
1
0
1
Mode Description
Normal Mode
Automatic Echo. Receiver input is connected to the TXD pin.
Local Loopback. Transmitter output is connected to the Receiver input.
Remote Loopback. RXD pin is internally connected to the TXD pin.
Asynchronous (SYNC=0)
1 stop bit
1.5 stop bits
2 stop bits
Reserved
0
1
0
1
x
x
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Synchronous (SYNC=1)
1 stop bit
Reserved
2 stop bits
Reserved
0xE and 0xF):
ATUC64/128/256L3/4U
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