ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 505

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.8.5
Name:
Access Type:
Offset:
Reset Value:
• SPIENS: SPI Enable Status
• UNDES: Underrun Error Status (Slave Mode Only)
• TXEMPTY: Transmission Registers Empty
• NSSR: NSS Rising
• OVRES: Overrun Error Status
• MODF: Mode Fault Error
• TDRE: Transmit Data Register Empty
• RDRF: Receive Data Register Full
32142A–12/2011
31
23
15
7
-
-
-
-
1: This bit is set when the SPI is enabled.
0: This bit is cleared when the SPI is disabled.
1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register.
0: This bit is cleared when the SR register is read.
1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the
completion of such delay.
0: This bit is cleared as soon as data is written in TDR.
1: A rising edge occurred on NSS pin since last read.
0: This bit is cleared when the SR register is read.
1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since
the last read of the RDR.
0: This bit is cleared when the SR register is read.
1: This bit is set when a Mode Fault occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when the last data written in the TDR register has been transferred to the serializer.
0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
0: No data has been received since the last read of RDR
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x10
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
OVRES
27
19
11
3
-
-
-
UNDES
MODF
ATUC64/128/256L3/4U
26
18
10
2
-
-
TXEMPTY
TDRE
25
17
9
1
-
-
SPIENS
NSSR
RDRF
24
16
8
0
-
505