ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 905

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Notes:
35.6.3
Table 35-13. Phase Locked Loop Characteristics
Note:
35.6.4
Table 35-14. Digital Frequency Locked Loop Characteristics
Notes:
32142A–12/2011
Symbol
f
f
I
t
Symbol
f
f
I
t
t
OUT
IN
PLL
STARTUP
OUT
REF
DFLL
STARTUP
LOCK
1. Nominal crystal cycles.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively.
Phase Locked Loop (PLL) Characteristics
Digital Frequency Locked Loop (DFLL) Characteristics
cess technology. These values are not covered by test limits in production.
cess technology. These values are not covered by test limits in production.
cess technology. These values are not covered by test limits in production.
Parameter
Output frequency
Input frequency
Current consumption
Startup time, from enabling
the PLL until the PLL is
locked
Parameter
Output frequency
Reference frequency
FINE resolution step
Frequency drift over voltage
and temperature
Accuracy
Power consumption
Startup time
Lock time
(2)
(2)
(1)
(1)
(2)
(2)
Conditions
f
f
Conditions
FINE > 100, all COARSE values
Open loop mode
FINE lock, f
ACCURATE lock, f
RCSYS/2, SSG disabled
FINE lock, f
disabled
ACCURATE lock, f
dither clk RCSYS/2, SSG disabled
Within 90% of final values
f
f
clock = RCSYS/2, SSG disabled
IN
IN
REF
REF
= 4MHz
= 16MHz
= 32kHz, ACCURATE lock, dithering
= 32kHz, FINE lock, SSG disabled
REF
REF
= 8-150kHz, SSG
= 32kHz, SSG disabled
REF
REF
= 32kHz, dither clk
= 8-150kHz,
(3)
ATUC64/128/256L3/4U
Min
20
Min
8
40
4
See
0.38
35-4
0.06
Typ
Typ
0.1
0.2
0.1
200
155
28
25
Figure
8
8
Max
240
Max
150
150
100
16
0.5
0.5
1
1
µA/MHz
µA/MHz
MHz
Unit
MHz
kHz
Unit
mS
µs
µs
%
%
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