ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 540

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.8.8
22.8.8.1
Figure 22-14. A Write Transfer with 10-bit Addressing
22.8.8.2
Figure 22-15. A Read Transfer with 10-bit Addressing
22.8.9
32142A–12/2011
S
1
SLAVE ADDRESS
1
Ten Bit Addressing
SMBus Mode
1
1st 7 bits
Master Transmitter
Master Receiver
1
0
S
X
1
X
SLAVE ADDRESS
1
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In
white boxes are driven by the slave.
To perform a master transmitter transfer:
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be written to one when the address phase of the transfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
RW A1
SMBus mode is enabled and disabled by writing to the SMEN and SMDIS bits in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
0
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,
2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout values to ensure progress and throughput on
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
1
Figure 22-14
1st 7 bits
the bus. These timeout values must be written into SMBTR.
Address (ARA) and Host Header (HH) Address.
1
desired address and NBYTES value.
NBYTES=0 and the desired address.
desired address and NBYTES value.
0
X
SLAVE ADDRESS
X
2nd byte
and
RW A1
0
Figure
SLAVE ADDRESS
22-15, the grey boxes represent signals driven by the master, the
A2
2nd byte
Sr
1
SLAVE ADDRESS
1
1
1st 7 bits
1
A2
0
DATA
X
ATUC64/128/256L3/4U
X
A
RW A3
1
DATA
DATA
A
AA
P
DATA
A
P
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