ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 717

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.6.10
29.6.11
32142A–12/2011
Analog Compare Mode
Interrupt Operation
Channels are enabled by writing a one to the corresponding bit in the Channel Enable Register
(CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register
(CHDR). Active channels are listed in the Channel Status Register (CHSR).
When a conversion sequence is started, all enabled channels will be converted in one sequence
and the result will be placed in the Last Converted Data Register (LCDR) with the channel num-
ber used to produce the result. It is important to read out the results while the conversion
sequence is ongoing, as new values will automatically overwrite any old value and the old value
will be lost if not previously read by the user.
If the Analog-to-Digital Converter cell is inactive when starting a conversion sequence, the con-
version logic will wait a configurable number of CLK_ADC cycles as defined in the startup time
field in the ADC Configuration Register (ACR). After the cell is activated all enabled channels is
converted one by one until no more enabled channels exist. The conversion sequence converts
each enabled channel in order starting with the channel with the lowest channel number. If the
ACR.SLEEP bit is one, the Analog-to-Digital Converter cell is deactivated after the conversion
sequence has finished.
For each channel converted, the ADCIFB waits a Sample and Hold number of CLK_ADC cycles
as defined in the SHTIM field in ACR, and then instructs the Analog-to-Digital Converter cell to
start converting the analog voltage. The ADC cell requires 10 CLK_ADC cycles to actually con-
vert the value, so the total time to convert a channel is Sample and Hold + 10 CLK_ADC cycles.
The ADCIFB can test if the converted values, as they become available, are below, above, or
inside a specified range and generate interrupt requests based on this information. This is useful
for applications where the user wants to monitor some external analog signal and only initiate
actions if the value is above, below, or inside some specified range.
The Analog Compare mode is enabled by writing a one to the Analog Compare Enable (ACE) bit
in the Mode Register (MR). The values to compare must be written to the Low Value (LV) field
and the High Value (HV) field in the Compare Value Register (CVR). The Analog Compare
mode will, when enabled, check all enabled channels against the pre-programmed high and low
values and set status bits.
To generate an interrupt request if a converted value is below a limit, write the limit to the
CVR.LV field and enable interrupt request on the Compare Lesser Than (CLT) bit by writing a
one to the corresponding bit in the Interrupt Enable Register (IER). To generate an interrupt
request if a converted value is above a limit, write the limit to the CVR.HV field and enable inter-
rupt for Compare Greater Than (CGT) bit. To generate an interrupt request if a converted value
is inside a range, write the low and high limit to the LV and HV fields and enable the Compare
Else (CELSE) interrupt. To generate an interrupt request if a value is outside a range, write the
LV and HV fields to the low and high limits of the range and enable CGT and CLT interrupts.
Note that the values written to LV and HV must match the resolution selected in the ADC Config-
uration Register (ACR).
Interrupt requests are enabled by writing a one to the corresponding bit in the Interrupt Enable
Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). Enabled interrupts can be read from the Interrupt Mask Register (IMR). Active
interrupt requests, but potentially masked, are visible in the Interrupt Status Register (ISR). To
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