ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 573

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32142A–12/2011
Table 23-5.
Event
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set,
SR.STREN and SR.SOAM
are set.
Repeated Start received
after being addressed
Stop received after being
addressed
Start, Repeated Start, or
Stop received in illegal
position on bus
Data is to be received in
slave receiver mode,
SR.STREN is set, and RHR
is full
Data is to be transmitted in
slave receiver mode,
SR.STREN is set, and THR
is empty
Data is to be received in
slave receiver mode,
SR.STREN is cleared, and
RHR is full
Data is to be transmitted in
slave receiver mode,
SR.STREN is cleared, and
THR is empty
SMBus timeout received
Slave transmitter in SMBus
PEC mode has transmitted
a PEC byte, that was not
identical to the PEC
calculated by the master
receiver.
Slave receiver discovers
SMBus PEC Error
Bus Events
Effect
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction (updating is done one
CLK_TWIS cycle after address match bit is set).
Slave stretches TWCK immediately after transmitting the address
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared.
Slave enters appropriate transfer direction mode and data transfer
can commence.
SR.REP set.
SR.TCOMP unchanged.
SR.STO set.
SR.TCOMP set.
SR.BUSERR set.
SR.STO and SR.TCOMP may or may not be set depending on the
exact position of an illegal stop.
TWCK is stretched until RHR has been read.
TWCK is stretched until THR has been written.
TWCK is not stretched, read data is discarded.
SR.ORUN is set.
TWCK is not stretched, previous contents of THR is written to bus.
SR.URUN is set.
SR.SMBTOUT is set.
TWCK and TWD are immediately released.
Master receiver will transmit a NAK as usual after the last byte of a
master receiver transfer.
Master receiver will retry the transfer at a later time.
SR.SMBPECERR is set.
NAK returned after the data byte.
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