ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 596

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.6.6
24.6.7
32142A–12/2011
Mono
Holding Registers
Figure 24-3. IISC Clocks Generation
When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel
is duplicated to the right output channel.
When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left
channel is duplicated to the right channel.
The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding
Register (THR). RHR and THR are used to access audio samples for both audio channels.
When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the
Status Register (SR) is set. Reading the RHR register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous
data word has been read from the RHR register. Then, the Receive Overrun bit in the Status
Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the cur-
rent receive channel number.
When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is
set. Writing into the THR register will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has
been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be
set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit
channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is trans-
mitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current
transmit channel number is transmitted.
MR.IMCKMODE
MR.MODE = SLAVE
ISCK pin input
IWS pin input
GCLK_IISC
CR.CKEN/CKDIS
0
1
enable
Clock
0
1
0
1
CR.CKEN/CKDIS
MR.IMCKMODE
enable
Clock
divider
Clock
ATUC64/128/256L3/4U
divider
Clock
MR.IMCKFS
MR.DATALENGTH
MR.DATALENGTH
IMCK pin output
ISCK pin output
Internal
bit clock
Internal
word clock
IWS pin output
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