ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 253

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.5.4.8
14.5.4.9
32142A–12/2011
Wake from sleep modes
Accuracy
DFLLIF can provide a clock with the energy spread in the frequency domain. This is done by
adding or subtracting values from the FINE value. SSG is enabled by writing a one to the Enable
bit (EN) in the DFLLn Spread Spectrum Generator Control Register ( DFLLnSSG).
A generic clock sets the rate at which the SSG changes the frequency of the DFLL clock to gen-
erate a spread spectrum (CLK_DFLLIF_DITHER). This is the same clock used by the dithering
mechanism. The frequency of this clock should be higher than f
can lock. Please refer to the Generic clocks section for details.
Optionally, the clock ticks can be qualified by a Pseudo Random Binary Sequence (PRBS) if the
PRBS bit in DFLLnSSG is one. This reduces the modulation effect of CLK_DFLLIF_DITHER fre-
quency onto f
The amplitude of the frequency variation can be selected by setting the SSG Amplitude field
(AMPLITUDE) in DFLLnSSG. If AMPLITUDE is zero the SSG will toggle on the LSB of the FINE
value. If AMPLITUDE is one the SSG will add the sequence {1,-1, 0} to FINE.
The step size of the SSG is selected by writing to the SSG Step Size field (STEPSIZE) in
DFLLnSSG. STEPSIZE equal to zero or one will result in a step size equal to one. If the step
size is set to n, the output value from the SSG will be incremented/decremented by n on every
tick of the source clock.
The Spread Spectrum Generator is available in both open and closed loop mode.
When spread spectrum is enabled in closed loop mode, and the AMPLITUDE is high, an over-
flow/underflow in FINE is more likely to occur.
Figure 14-5. Spread Spectrum Generator Block Diagram.
The DFLLIF may optionally reset its lock bits when waking from a sleep mode which disables the
DFLL. This is configured by the Lose Lock After Wake (LLAW) bit in DFLLnCONF register. If
DFLLnCONF.LLAW is written to zero the DFLL will be re-enabled and start running with the
same configuration as before going to sleep even if the reference clock is not available. The
locks will not be lost. When the reference clock has restarted, the FINE tracking will quickly com-
pensate for any frequency drift during sleep. If a one is written to DFLLnCONF.LLAW before
going to a sleep mode where the DFLL is turned off, the DFLLIF will lose all its locks when wak-
ing up, and needs to regain these through the full lock sequence.
There are mainly three factors that decide the accuracy of the f
obtain maximum accuracy when fine lock is achieved.
CLK_DFLLIF_DITHER
DFLL
.
Binary Sequence
Pseudorandom
PRBS
1
0
ATUC64/128/256L3/4U
Spread Spectrum
AMPLITUDE,
STEPSIZE
Generator
FINE
REF
DFLL
to ensure that the DFLLIF
. These can be tuned to
9
To DFLL
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