ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 537

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 22-10. User Sends Data While the Bus is Busy
Figure 22-11. Arbitration Cases
22.8.7
32142A–12/2011
Data from a Master
TWI DATA transfer
TWI DATA transfer
Data from TWI
(DADR + W + START + Write THR)
(DADR + W + START + Write THR)
Combined Transfers
ARBLST
TWCK
A transfer is programmed
TWCK
TWD
TWD
A transfer is programmed
TWCK
TWD
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause
a REPEATED START on the bus. The ability to generate such connected transfers allows arbi-
trary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is
done in master receiver mode, the CMDR.ACKLAST bit must also be controlled.
S
S
S
DATA sent by a master
1
1
1
Transfer is stopped
Bus is busy
0 0
0
0 0
1
STOP sent by the master
Transfer is kept
1 1
1 1
TWI stops sending data
Arbitration is lost
(DADR + W + START + Write THR)
Transfer is programmed again
Data from the master
Bus is busy
Transfer is kept
Bus is free
Bus is considered as free
Transfer is initiated
P
P
Bus is free
ATUC64/128/256L3/4U
Bus is considered as free
Transfer is initiated
START sent by the TWI
S
S
S
1
1
1
0
0 0
0
DATA sent by the TWI
1
0
1 1
The master stops sending data
1 1
Arbitration is lost
Data from the TWI
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