ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 896

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

35.3
Table 35-4.
35.4
32142A–12/2011
Symbol
f
f
f
f
f
f
f
f
f
f
f
f
f
CPU
PBA
PBB
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
Maximum Clock Frequencies
Power Consumption
Parameter
CPU clock frequency
PBA clock frequency
PBB clock frequency
GCLK0 clock frequency
GCLK1 clock frequency
GCLK2 clock frequency
GCLK3 clock frequency
GCLK4 clock frequency
GCLK5 clock frequency
GCLK6 clock frequency
GCLK7 clock frequency
GCLK8 clock frequency
GCLK9 clock frequency
Clock Frequencies
Table 35-3.
Note:
These parameters are given in the following conditions:
The values in
tions, except where noted:
Symbol
V
V
V
V
• V
• Temperature = -40°C to 85°C
• Operating conditions, internal core supply
VDDIO
VDDIN
VDDCORE
VDDANA
VDDCORE
– V
1. These values are based on simulation and characterization of other AVR microcontrollers
VDDIN
manufactured in the same process technology. These values are not covered by test limits in
production.
Parameter
DC supply peripheral I/Os
DC supply peripheral I/Os
and internal regulator
DC supply core
Analog supply voltage
= 1.62V to 1.98V
Table 35-5
Supply Rise Rates and Order
= 3.0V
Description
DFLLIF main reference, GCLK0 pin
DFLLIF dithering and SSGreference, GCLK1 pin
AST, GCLK2 pin
PWMA, GCLK3 pin
CAT, ACIFB, GCLK4 pin
GLOC and GCLK5 pin
ABDACB, IISC, and GCLK6 pin
USBC and GCLK7 pin
PLL0 source clock and GCLK8 pin
FREQM, GCLK0-8, GCLK9 pin
are measured values of power consumption under the following condi-
0.002
Min
0
0
0
(1)
(Figure
Max
2.5
2.5
2.5
2.5
ATUC64/128/256L3/4U
35-1) - this is the default configuration
V/µs
V/µs
V/µs
V/µs
Unit
Rise Rate
Min
Slower rise time requires
external power-on reset
circuit.
Rise before or at the same
time as VDDIO
Rise together with
VDDCORE
Comment
Max
140
150
50
50
50
50
50
20
50
80
50
50
50
Units
MHz
896