ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 722

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ATUC128L4U

Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC128L4U

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Price
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29.7.4
29.7.5
32142A–12/2011
Resistive Touch Screen Sequencer
Pen Detect
The Resistive Touch Screen Sequencer is responsible for applying voltage to the resistive touch
screen films as described in
output value of the ADP and AD pins. This allows the Resistive Touch Screen Sequencer to add
a voltage gradient on one film while keeping the other film floating so a touch can be measured.
The Resistive Touch Screen Sequencer will when measuring the vertical position, apply VDD
and GND to the pins connected to X
measurement of Y
non ideal pad drivers, the actual voltage of X
VDD and GND can be used in the contact point calculation to increase accuracy. See second
formula in
When the vertical values are converted the same setup is applies for the second axes, by setting
X
details.
If no contact is applied to the resistive touch screen films, any resistive touch screen conversion
result will be undefined as the film being measured is floating. This can be avoided by enabling
Pen Detect and only trigger resistive touch screen conversions when the Pen Contact
(PENCNT) status bit in the Status Register (SR) is one. Pen Detect is enabled by writing a one
to the Pen Detect (PENDET) bit in the Mode Register (MR).
When Pen Detect is enabled, the ADCIFB grounds the vertical panel by applying GND to X
X
will in this mode be tristated. Since there is no contact, no current is flowing and there is no
related power consumption. As soon as a contact occurs, GND will propagate to Y
down Y
A programmable debouncing filter can be used to filter out false pen detects because of noise.
The debouncing filter is programmable from one CLK_ADC period and up to 2
ods. The debouncer length is set by writing to the PENDBC field in MR.
P
M
and X
and polarizes the horizontal panel by enabling pull-up on the pin connected to Y
P
, allowing the contact to be registered by the ADCIFB.
M
Section
in tristate mode and applying VDD and GND to Y
P
29.7.2.
can proceed without interference. To compensate for ADC offset errors and
Section
P
29.7.2. This is done by controlling the output enable and the
and X
M
P
. The Y
and X
P
M
ATUC64/128/256L3/4U
and Y
is measured as well, so the real values for
M
P
and Y
pins are put in tristate mode so the
M
. Refer to
15
Section 29.8.3
CLK_ADC peri-
P
. The Y
M
by pulling
P
M
and
722
pin
for

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