ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 621

• Manufacturer Part Number: ATUC128L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC128L4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.7
25.6.8
25.6.9
25.6.10
25.6.10.1
32142A–12/2011
Open Drain Mode
Synchronization
Interrupts
Peripheral Events
Input Peripheral Events
Some pins can be used in open drain mode, allowing the PWMA waveform to toggle between
0V and up to 5V on these pins. In this mode the PWMA will drive the pin to zero or leave the out-
put open. An external pullup can be used to pull the pin up to the desired voltage.
To enable open drain mode on a pin the PWMAOD function must be selected instead of the
PWMA function in the I/O Controller. Please refer to the Module Configuration chapter for infor-
mation about which pins are available in open drain mode.
Both the timebase counter and the spread spectrum counter can be reset and the duty cycle
registers can be written through the user interface of the module. This requires a synchroniza-
tion between the PB and GCLK clock domains, which takes a few clock cycles of each clock
domain. The BUSY bit in SR indicates when the synchronization is ongoing. Writing to the mod-
ule while the BUSY bit is set will result in discarding the new value.
Note that the duty cycle registers will not be updated with the new values until the timebase
counter reaches its top value, in order to avoid glitches. The BUSY bit in SR will always be set
during this updating and synchronization period.
When the timebase counter overflows, the Timebase Overflow bit in the Status Register
(SR.TOFL) is set. If the corresponding bit in the Interrupt Mask Register (IMR) is set, an interrupt
request will be generated.
Since the user needs to wait until the user interface is available between each write due to syn-
chronization, a READY bit is provided in SR, which can be used to generate an interrupt
request.
The interrupt request will be generated if the corresponding bit in IMR is set. Bits in IMR are set
by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by
writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt
request remains active until the corresponding bit in SR is cleared by writing a one to the corre-
sponding bit in the Status Clear Register (SCR).
The pre-defined channels support input peripheral events from the Peripheral Event System.
Input peripheral events must be enabled by writing a one to the corresponding bit in the Channel
Event Enable Registers (CHEERs) before peripheral events can be used to control the duty
cycle value. Each bit in the register corresponds to one channel, where bit 0 corresponds to
channel 0 and so on. Both the increase and decrease events are enabled for the corresponding
channel when a bit in the CHEER register is set.
An increase or decrease event (event_incr/event_decr) can either increase or decrease the duty
cycle value by one in a PWM period. The events are taken into account when the common time-
base counter reaches its top. The behavior is defined by the Channel Event Response Register
(CHERR). Each bit in the register corresponds to one channel, where bit 0 corresponds to chan-
nel 0 and so on. If the bit in CHERR is set to 0 (default) for a channel, the increase event will
increase the duty cycle value and the decrease event will decrease the duty cycle value for that
channel. If the bit is set to 1, the increase and decrease event will have reverse function so that
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