ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 624

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ATUC128L4U

Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC128L4U

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATUC128L4U-AUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATUC128L4U-AUT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
25.7.1
Name:
Access Type:
Offset :
Reset Value:
32142A–12/2011
SPREAD: Spread Spectrum Limit Value
TOP: Timebase Counter Top Value
TCLR: Timebase Clear
EN: Module Enable
31
23
15
7
-
-
The spread spectrum limit value, together with the TOP field, defines the range for the spread spectrum counter. It is introduced
in order to achieve constant varying duty cycles on the output PWM waveforms. Refer to
The top value for the timebase counter. The value written to this field will update the least significant 8 bits of the TVR.TOP field
in case only 8-bits resolution is required. The 4 most significant bits of TVR.TOP will be written to 0. When the TVR.TOP field is
written, this CR.TOP field will also be updated with only the least significant 8 bits of TVR.TOP field.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the timebase counter.
This bit is always read as zero.
0: The PWMA is disabled
1: The PWMA is enabled
Control Register
30
22
14
6
-
-
CR
Read/Write
0x00
0x00000000
29
21
13
5
-
-
28
20
12
4
-
-
SPREAD[7:0]
TOP
27
19
11
3
-
-
ATUC64/128/256L3/4U
26
18
10
2
-
-
Section25.6.3
TCLR
25
17
9
1
-
for more information.
SPREAD[8]
EN
24
16
8
0
624

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