MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 10

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.10.1
6.2.10.1.1
6.2.10.1.2
7.1
7.1.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.4.1
7.4.2
7.5
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
x
Overview............................................................................................................. 7-1
PLL Operation .................................................................................................... 7-2
PLL Port List....................................................................................................... 7-4
Timing Relationships .......................................................................................... 7-4
PLL Power Supply Filter Circuit ........................................................................ 7-6
Overview............................................................................................................. 8-1
Interface Features................................................................................................ 8-1
I
I
Programming Model ........................................................................................... 8-6
2
2
C System Configuration................................................................................... 8-3
C Protocol ........................................................................................................ 8-3
Module Base Address Register (MBAR) ....................................................... 6-4
Reset Status Register (RSR) ........................................................................... 6-5
Software Watchdog Timer.............................................................................. 6-6
System Protection Control Register (SYPCR) ............................................... 6-8
Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9
Software Watchdog Service Register (SWSR)............................................... 6-9
PLL Clock Control for CPU STOP Instruction ............................................ 6-10
Pin Assignment Register (PAR) ................................................................... 6-10
Bus Arbitration Control ................................................................................ 6-11
PLL:PCLK Ratios........................................................................................... 7-2
Reset/Initialization .......................................................................................... 7-2
Normal Mode.................................................................................................. 7-2
Reduced-Power Mode..................................................................................... 7-3
PLL Control Register (PLLCR)...................................................................... 7-3
PCLK, PSTCLK, and BCLKO ....................................................................... 7-4
RSTI Timing ................................................................................................... 7-5
Arbitration Procedure ..................................................................................... 8-4
Clock Synchronization.................................................................................... 8-5
Handshaking ................................................................................................... 8-5
Clock Stretching ............................................................................................. 8-5
Default Bus Master Park Register (MPARK) .......................................... 6-11
Arbitration for Internally Generated Transfers (MPARK[PARK])...... 6-12
Arbitration between Internal and External Masters
for Accessing Internal Resources ......................................................... 6-14
Phase-Locked Loop (PLL)
MCF5407 User’s Manual
CONTENTS
I
2
Chapter 7
Chapter 8
C Module
Title
Number
Page