MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 155

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In Table 4-10 the current state is modified.
Read miss
Read hit
Write miss
(copyback)
Write miss
(write-through)
Write hit
(copyback)
Write hit
(write-through)
Access
Table 4-10. Data Cache Line State Transitions (Current State Modified)
Read miss
Read hit
Write miss (copyback)
Write miss (write-through)
Write hit (copyback)
Write hit (write-through)
Cache invalidate
Cache push
Cache push
Table 4-9. Data Cache Line State Transitions (Current State Valid)
Access
WD3 Write data to memory;
WD4 Write data to memory and to cache;
CD1 Push modified line to buffer;
CD2 Supply data to processor;
CD3 Push modified line to buffer;
CD4 Write data to cache;
read new line from memory and update cache;
supply data to processor;
write push buffer contents to memory;
go to valid state.
stay in modified state.
read new line from memory and update cache;
write push buffer contents to memory;
stay in modified state.
stay in modified state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
stay in modified state.
go to valid state.
Cache mode changed for the region corresponding to this line. To avoid this state,
execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching modes.
(C,W)V1 Read new line from memory and update cache;
(C,W)V2 Supply data to processor;
CV3
WV3
CV4
WV4
(C,W)V5 No action;
(C,W)V6 No action;
(C,W)V7 No action;
Chapter 4. Local Memory
supply data to processor; stay in valid state.
stay in valid state.
Read new line from memory and update cache;
write data to cache;
go to modified state.
Write data to memory;
stay in valid state.
Write data to cache;
go to modified state.
Write data to memory and to cache;
stay in valid state.
go to invalid state.
go to invalid state.
stay in valid state.
Response
Response
Cache Operation Summary
4-31