MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 296

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Synchronous Operation
latency (SCAS assertion to data out), this value is also 2 CLKIN cycles. Notice that
are executed until the last data is read. A
data transfer.
Figure 11-19 shows the burst write operation. In this example, DACR[CASL] = 01, which
creates an SRAS-to-SCAS delay (t
upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read
cycle with the same t
SDRAM cycle until the precharge-to-
11-28
RAS[0] or [1]
CAS[3:0]
DRAMW
A[31:0]
D[31:0]
CLKIN
SRAS
SCAS
ACTV
t
RCD
Row
Figure 11-18. Burst Read SDRAM Access
RCD.
= 2
NOP
The next bus cycle is initiated sooner, but cannot begin an
Column Column Column
MCF5407 User’s Manual
RCD
ACTV
t
CASL
) of 2 CLKIN cycles. Note that data is available
PALL
READ
= 2
delay completes.
command is executed one cycle after the last
Column
NOP
NOP
t
EP
PALL
NOP
s