MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 145

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.10 Cache Registers
This section describes the MCF5407 implementation of the Version 4 cache registers.
4.10.1 Cache Control Register (CACR)
The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the
MOVEC register instruction and can be read or written from the debug facility. A hardware
reset clears CACR, which disables the cache; however, reset does not affect the tags, state
information, or data in the cache.
Table 4-4 describes CACR fields.
31
30
29
28
Bits
Reset
Reset
Field DEC DW DESB DDPI DHLCK
Field IEC
R/W
R/W
Rc
Name
DESB
DDPI
DEC
31
15
DW
— DNFB IDPI IHLCK IDCM
30
14
Enable data cache.
0 Cache disabled. The data cache is not operational, but data and tags are preserved.
1 Cache enabled.
Data default write-protect. For normal operations that do not hit in the RAMBARs or ACRs, this
field defines write-protection. See Section 4.9.1, “Caching Modes.”
0 Not write protected.
1 Write protected. Write operations cause an access error exception.
Enable data store buffer. Affects the precision of transfers. CACR[DESB] has precedence over
CACR[9–8] and ACRn[9–8]; therefore, the store buffer must be disabled to use imprecise mode.
0 Imprecise-mode, write-through or cache-inhibited writes bypass the store buffer and generate
1 The four-entry FIFO store buffer is enabled; to maximize performance, this buffer defers
Precise-mode, cache-inhibited accesses always bypass the store buffer. Precise and imprecise
modes are described in Section 4.9.2, “Cache-Inhibited Accesses.”
Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified,
bus cycles directly. Section 4.9.5.2.1, “Push and Store Buffers,” describes the associated
performance penalty.
pending imprecise-mode, write-through or cache-inhibited writes.
then invalidated.
then left valid.
29
13
Figure 4-8. Cache Control Register (CACR)
28
12
Table 4-4. CACR Field Descriptions
27
11
Chapter 4. Local Memory
26
10
DDCM
Write (R/W by debug module)
Write (R/W by debug module)
0000_0000_0000_0000
0000_0000_0000_0000
—
25
9
DCINVA
ICINVA
0x002
24
8
Description
23
7
—
20
—
BEC BCINVA
19
Cache Registers
18
17
—
4-21
16
0