MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 316

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Transfer Overview
12.3 DMA Transfer Overview
The DMA module usually transfers data faster than the ColdFire core can under software
control. The term ‘direct memory access’ refers to peripheral device’s ability to access
system memory directly, greatly improving overall system performance. The DMA module
consists of four independent, functionally equivalent channels, so references to DMA in
this chapter apply to any of the channels. It is not possible to implicitly address all four
channels at once. The MCF5407 on-chip peripherals do not support single-address
transfers.
The processor generates DMA requests internally by setting DCR[START]; a device can
generate a DMA request externally by using DREQ pins. The processor can program bus
bandwidth for each channel. The channels support cycle-steal and continuous transfer
modes; see Section 12.5.1, “Transfer Requests (Cycle-Steal and Continuous Modes).”
The DMA controller supports dual- and single-address transfers as follows. In both, the
DMA channel supports 32 address bits and 32 data bits.
12-4
Single/dual cycle access
DMA 0 acknowledge configuration
DMA 1 acknowledge configuration
• Dual-address transfers—A dual-address transfer consists of a read followed by a
write and is initiated by an internal request using the START bit or by an external
device using DREQ. Two types of transfer can occur, a read from a source device or
a write to a destination device; see Figure 12-3.
MCF5307 Function
Figure 12-2. MCF5307/MCF5407 TM[2:0] Pin Remapping
Figure 12-3. Dual-Address Transfer
DMA
DMA
TM0
TM1
TM2
Control and Data
Control and Data
Pin
MCF5407 User’s Manual
TM0
TM1
TM2
Pin
Peripheral
Peripheral
Memory/
Memory/
DMA 0 acknowledge
DMA 1 acknowledge
Single/dual cycle access
MCF5407 Function