MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 117

• Manufacturer Part Number: MCF5407CAI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407CAI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-FQFP
• Processor Series: MCF540x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Program Memory Size: 8 KB
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 162 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 1.8 V to 3.3 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TAS
Operation:
Assembler Syntax: TAS <ea>x
Attributes:
Description: Tests and sets the byte operand addressed by the effective address field. The
instruction tests the current value of the operand and sets the N and Z condition code bits
appropriately. TAS also sets the high-order bit of the operand. The operand uses a
read-modify-write memory cycle that completes the operation without interruption. This
instruction supports use of a flag or semaphore to coordinate several processors.
Condition Codes:
Instruction Fields:
Instruction
Format:
—
X
• Effective address field—specifies the destination location; the possible data alterable
Addressing Mode
addressing modes are listed in the table below.
N
∗
(d
(Ax) +
– (Ax)
(Ax)
16
Dx
Ax
,Ax)
15
Z
∗
0
Operand sizes supported
14
1
V
0
Opcode present
Destination Tested → CCR; 1 → bit 7 of Destination
Size = byte
Mode
13
010
011
100
101
0
—
—
TAS
C
0
12
0
reg. number:Ax
reg. number:Ax
reg. number:Ax
reg. number:Ax
X Not affected
N Set if the msb of the operand is currently set; cleared otherwise
Z Set if the operand was zero; cleared otherwise
V Always cleared
C Always cleared
Register
11
Chapter 2. ColdFire Core
1
Test and Set an Operand
—
—
10
0
ColdFire Instruction Set Architecture Enhancements
1
9
V2, V3 Core
Addressing Mode
0
8
No
(d
(d
—
(d
#<data>
(xxx).W
(xxx).L
8
8
1
7
16
,PC,Xi)
,Ax,Xi)
,PC)
1
6
5
Mode
MODE
110
111
111
EFFECTIVE ADDRESS
—
—
—
4
V4 Core
Yes
.b
3
reg. number:Ax
Register
000
001
2
—
—
—
REGISTER
TAS
1
2-51
0