MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 53
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Module Description
1.3.2.1 16-Kbyte Instruction Cache/8-Kbyte Data Cache
The MCF5407 Harvard architecture includes a 16-Kbyte instruction cache and an 8-Kbyte
data cache. These four-way, set-associative caches provide pipelined, single-cycle access
on cached instructions and operands.
As with all ColdFire caches, the cache controllers implement a non-lockup, streaming
design. The use of processor-local memories decouples performance from external
memory speeds and increases available bandwidth for external devices or the on-chip
4-channel DMA.
Both caches implement line-fill buffers to optimize 16-byte line burst accesses.
Additionally, the data cache supports copyback, write-through, or cache-inhibited modes.
A 4-entry, 32-bit buffer is used for cache line push operations and can be configured for
deferred write buffering in write-through or cache-inhibited modes.
The INTOUCH instruction can be used to prefetch instructions that, when used with the
cache locking feature, cannot be displaced from the instruction cache by instruction cache
misses. This function may be desirable in systems where deterministic real-time
performance is critical.
1.3.2.2 Internal 2-Kbyte SRAMs
Two 2-Kbyte on-chip SRAM modules are also connected to the Harvard memory
architecture and provide pipelined, single-cycle access to memory regions mapped to these
devices. Each memory can be independently mapped to any 0-modulo-2K location in the
4-Gbyte address space and can be configured either for instruction or data accesses.
Time-critical functions can be mapped onto the instruction memory bus, while the system
stack or heavily-referenced data operands can be mapped onto the data bus.
1.3.3 DRAM Controller
The MCF5407 DRAM controller provides a direct interface for up to two blocks of DRAM.
The controller supports 8-, 16-, or 32-bit memory widths and can easily interface to PC-100
DIMMs. A unique addressing scheme allows for increases in system memory size without
rerouting address lines and rewiring boards. The controller operates in normal mode or in
page mode and supports SDRAMs and EDO DRAMs.
1.3.4 DMA Controller
The MCF5407 provides four fully programmable DMA channels for quick data transfer.
Dual- and single-address modes support bursting and cycle steal. Data transfers are 32 bits
long with packing and unpacking supported along with an auto-alignment option for
efficient block transfers. Automatic block transfers from on-chip serial UARTs are also
supported through the DMA channels.
Chapter 1. Overview
1-9
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