MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 36
![IC MPU 32B 220MHZ COLDF 208-FQFP](/photos/12/22/122277/mcf5407cai220_sml.jpg)
MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Organization
xxxvi
• Part II, “System Integration Module (SIM),” describes the system integration
— Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the
— Chapter 4, “Local Memory.” This chapter describes the MCF5407
— Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug
module, which provides overall control of the bus and serves as the interface
between the ColdFire core processor complex and internal peripheral devices. It
includes a general description of the SIM and individual chapters that describe
components of the SIM, such as the phase-lock loop (PLL) timing source, interrupt
controller for peripherals, configuration and operation of chip selects, and the
SDRAM controller.
— Chapter 6, “SIM Overview,” describes the SIM programming model, bus
— Chapter 7, “Phase-Locked Loop (PLL),” describes configuration and operation
— Chapter 8, “I2C Module,” describes the MCF5407 I
— Chapter 9, “Interrupt Controller,” describes operation of the interrupt controller
— Chapter 10, “Chip-Select Module,” describes the MCF5407 chip-select
— Chapter 11, “Synchronous/Asynchronous DRAM Controller Module,”
MCF5407 multiply/accumulate unit, which executes integer multiply,
multiply-accumulate, and miscellaneous register instructions. The MAC is
integrated into the operand execution pipeline (OEP).
implementation of the ColdFire V4 local memory specification. It consists of the
two following major sections.
– Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM
– Section 4.7, “Cache Overview,” describes the MCF5407 cache
support in the MCF5407. This revision of the ColdFire debug architecture
encompasses earlier revisions.
arbitration, and system-protection functions for the MCF5407.
of the PLL module. It describes in detail the registers and signals that support the
PLL implementation.
protocol, clock synchronization, and the registers in the I
It also provides extensive programming examples.
portion of the SIM. Includes descriptions of the registers in the interrupt
controller memory map and the interrupt priority scheme.
implementation, including the operation and programming model, which
includes the chip-select address, mask, and control registers.
describes configuration and operation of the synchronous/asynchronous DRAM
(SRAM) implementation. It covers general operations, configuration, and
initialization. It also provides information and examples showing how to
minimize power consumption when using the SRAM.
implementation, including organization, configuration, and coherency. It
describes cache operations and how the cache interacts with other memory
structures.
MCF5407 User’s Manual
2
C module, including I
2
C programing model.
2
C
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