MCF5407CAI220 Freescale Semiconductor, MCF5407CAI220 Datasheet - Page 361
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MCF5407CAI220
Manufacturer Part Number
MCF5407CAI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Specifications of MCF5407CAI220
Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-FQFP
Processor Series
MCF540x
Core
ColdFire V4
Data Bus Width
32 bit
Program Memory Size
8 KB
Data Ram Size
4 KB
Maximum Clock Frequency
162 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 3.3 V
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale
Quantity:
789
Company:
Part Number:
MCF5407CAI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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14.3.16 UART Divider Upper/Lower Registers (UDUn/UDLn)
The UDUn registers (formerly called UBG1n) holds the MSB, and the UDLn registers
(formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to
provide a divider to CLKIN for transmitter/receiver operation, as described in
Section 14.5.1.2.1, “CLKIN Baud Rates.”
Bits
6–3
Address
Address
7
2
1
0
Reset
Reset
Field
Field
R/W
R/W
COS
—
DB
FFULL/
RxRDY
TxRDY
Name
7
7
Change-of-state. Not used by UART1 in modem mode.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
Reserved, should be cleared.
Delta break. Not used by UART1 in modem mode.
0 No new break-change condition to report. Section 14.3.10, “UART Command Registers (UCRn),”
1 The receiver detected the beginning or end of a received break.
RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY]
= 1. Duplicate of USRn[FFULL/RxRDY]. Used by UART1 in modem mode. If FFULL is enabled for
UART0 or UART1, DMA channels 2 or 3 are respectively interrupted when the FIFO is full.
Transmitter ready. This bit is the duplication of USRn[TxRDY]. Used by UART1 in modem mode.
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
1 The transmitter holding register is empty and ready to be loaded with a character.
The minimum value that can be loaded on the concatenation of
UDUn with UDLn is 0x0002. Both UDUn and UDLn are
write-only and cannot be read by the CPU.
describes the
loaded into the transmitter holding register when TxRDY = 0 are not sent.
Figure 14-19. UART Divider Upper Register (UDUn)
Figure 14-20. UART Divider Lower Register (UDLn)
Table 14-14. UISRn/UIMRn Field Descriptions
RESET BREAK
Chapter 14. UART Modules
MBAR + 0x1D8 (UDU0), 0x218 (UDU1)
MBAR + 0x1DC (UDL0), 0x21C (UDL1)
-
CHANGE INTERRUPT
NOTE:
Divider MSB
Divider LSB
0000_0000
0000_0000
Description
R/W
R/W
command.
Register Descriptions
0
0
14-19
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